Sensor IP Cores

IP Cores for Sony Pregius Sub-LVDS and MIPI CSI-2 image sensors

At a glance
  • Image sensor data deserialization and decoding
  • Software library for sensor configuration
  • Compatible with AMD FPGAs
  • Delivered as working reference design for fast development
 
IMX Pregius IP Core

IP Core for Sony Pregius Sub-LVDS image sensors

 
MIPI CSI-2 Receiver IP Core

IP Core for MIPI CSI-2 Imagers

A Sensor to Image product
A Sensor to Image product


Reduced time to market

Machine vision camera suppliers reduce time to market with transport layer IP Cores, and rely on Sensor to Image to keep up with both technological and standards advancements.
To stream images from the camera to the host, several modern standards of vision transport layers exist. The most powerful ones (GigE Vision, USB3, CoaXPress, ...) may however appear complex and evolving. Compressing months of development work, Sensor to Image’s IP Cores enable machine vision companies to build FPGA-based products following these standards, delivering the highest possible performance in a small footprint while minimizing development time.


IMX Pregius IP Core Description

The IMX Pregius from Sony is a series of widely used, high quality CMOS image sensors. S2I’s IMX Pregius IP Core supports these sensors, it is able to read their data as well as controlling them. It is delivered as a fully functioning reference design that is running on an agreed common delivery platform along with an FMC module compatible with S2I’s MVDK and standard FPGA evaluation kits. Together, they provide an easy way to design a camera.


MIPI CSI-2 IP Core Description

Image sensors with MIPI interface are not only used in mobile phones, but also in industrial and automotive applications. These applications often require an FPGA for control and further processing. This IP helps to interface MIPI sensors of different vendors to FPGAs. The IP relies on an existing D-PHY implementation, typically available from FPGA vendors. The IP is delivered as a fully functioning reference design that is running on an agreed common delivey platform along with a MIPI FMC module compatible with S2I’s MVDK and standard FPGA evaluation kits. Together, they provide an easy way to design a camera.


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