Sensor IP Cores

IP cores for Sony Pregius Sub-LVDS and MIPI CSI-2 image sensors

At a glance
  • Image sensor data deserialization and decoding
  • Software library for sensor configuration
  • Compatible with Xilinx FPGAs
  • Delivered with a reference design for fast development
 
IMX Pregius IP Core

IP core for Sony Pregius Sub-LVDS image sensors

 
MIPI CSI-2 Receiver IP Core

IP Core for MIPI CSI-2 Imagers

A Sensor to Image product
A Sensor to Image product


Reduced time to market

Machine vision camera suppliers reduce time to market with transport layer IP Cores, and rely on Sensor to Image to keep up with both technological and standards advancements.
To stream images from the camera to the host, several modern standards of vision transport layers exist. The most powerful ones (GigE Vision, USB3, CoaXPress, ...) may however appear complex and evolving. Compressing months of development work, Sensor to Image’s IP Cores enable machine vision companies to build FPGA-based products following these standards, delivering the highest possible performance in a small footprint while minimizing development time.


IMX Pregius IP Core Description

The IMX Pregius from Sony is a series of widely used, high quality CMOS image sensors. S2I’s IMX Pregius IP Core supports these sensors, it is able to read their data as well as controlling them. It is delivered as a reference design along with an FMC module compatible with S2I’s MVDK and standard FPGA evaluation kits. Together, they provide an easy way to design a camera.


MIPI CSI-2 IP Core Description

MIPI CSI-2 is one of the most widely used camera sensor interfaces. Many applications require the connection to an FPGA for advanced image pre-processing and further transfer to a host system. Sensor to Image’s MIPI CSI-2 Receiver IP core provides a solution for decoding video streams from CSI-2 sensors in a Xilinx FPGA. It uses a companion IP core, provided by Xilinx, implementing the MIPI D-PHY physical interface. The D-PHY receiver is connected to the CSI-2 sensor using the PHY-Protocol Interface (PPI). In order to shorten the development time, the MIPI CSI-2 Receiver IP core is delivered with a fully working reference design including Sensor to Image’s MVDK and an IMX274 MIPI FMC module.


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