IMX Pregius IP Core

IP core for Sony Pregius Sub-LVDS image sensors

At a glance
  • Sub-LVDS readout and decoding block
  • SPI-based sensor configuration module
  • Software library for sensor configuration
  • Free running or triggered readout modes

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A Sensor to Image product
A Sensor to Image product

Trigger Generator

The IMX sensor itself can be used in free running mode or in slave mode using the core’s timing and trigger generator. An SPI-based control interface enables sensor configuration, following the correct configuration timing.

IMX Pregius IP Core Description

The IMX Pregius from Sony is a series of widely used, high quality CMOS image sensors. S2I’s IMX Pregius IP Core supports these sensors, it is able to read their data as well as controlling them. It is delivered as a reference design along with an FMC module compatible with S2I’s MVDK and standard FPGA evaluation kits. Together, they provide an easy way to design a camera.

Control Registers

The functionality of the IP core is configured either by parameters at compile time, or by Control Registers using an AXI-Lite interface at run time. A C software library configures the sensor and the IP core.

SubLVDS Receiver and Deserializer

The SubLVDS Receiver and Deserializer block is connected to the sensor’s output pins and uses the FPGA IO cells to deserialize the image stream. This block is highly FPGA dependent and currently limited to AMD FPGAs. The parallel video stream can be cropped and is presented in a Camera Link-like format for further processing.


The IP core is delivered with a full reference design, including an FMC (FPGA Mezzanine Card), which forms the interface between the sensor and a standard FPGA evaluation board. The FMC module is FMC-LPC compliant and does all power and level adaptations required by the IMX CMOS sensor.