MIPI CSI-2 IP Core Description
MIPI CSI-2 is one of the most widely used camera sensor interfaces. Many applications require the connection to an FPGA for advanced image pre-processing and further transfer to a host system. Sensor to Image’s MIPI CSI-2 Receiver IP core provides a solution for decoding video streams from CSI-2 sensors in a AMD FPGA.
It uses a companion IP core, provided by AMD, implementing the MIPI D-PHY physical interface. The D-PHY receiver is connected to the CSI-2 sensor using the PHY-Protocol Interface (PPI).
In order to shorten the development time, the MIPI CSI-2 Receiver IP core is delivered with a fully working reference design including Sensor to Image’s MVDK and an IMX274 MIPI FMC module.
The core is delivered with a complete reference design for S2I’s MVDK with a Zynq Ultrascale+ FPGA and an IMX274 MIPI FMC module. Since the physical interface is abstracted by the AMD D-PHY core, it is easy to port the design to other FPGA platforms like for example the 7 series AMD FPGAs.