MIPI CSI-2 Receiver IP Core

IP Core for MIPI CSI-2 Imagers

At a glance
  • MIPI CSI-2 receiver and decoding block
  • Configurable number of MIPI Lanes
  • Using AMD D-PHY IP
  • Delivered with a reference design for fast development

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MIPI CSI-2 IP Core Description

MIPI CSI-2 is one of the most widely used camera sensor interfaces. Many applications require the connection to an FPGA for advanced image pre-processing and further transfer to a host system. Sensor to Image’s MIPI CSI-2 Receiver IP core provides a solution for decoding video streams from CSI-2 sensors in a AMD FPGA. It uses a companion IP core, provided by AMD, implementing the MIPI D-PHY physical interface. The D-PHY receiver is connected to the CSI-2 sensor using the PHY-Protocol Interface (PPI). In order to shorten the development time, the MIPI CSI-2 Receiver IP core is delivered with a fully working reference design including Sensor to Image’s MVDK and an IMX274 MIPI FMC module.


The core is delivered with a complete reference design for S2I’s MVDK with a Zynq Ultrascale+ FPGA and an IMX274 MIPI FMC module. Since the physical interface is abstracted by the AMD D-PHY core, it is easy to port the design to other FPGA platforms like for example the 7 series AMD FPGAs.

Main features

  • FPGA technology independent
  • PPI interface to connect to different D-PHY implementations
  • Configurable to 1, 2 or 4 data lanes
  • Any lane rate
  • RAW8, RAW10, RAW12, RAW14, RAW16 standard MIPI data types
  • Embedded data decoding
  • Direct output of reordered byte stream without pixel unpacking
  • AXI4-Lite slave control interface

Modules available

The MIPI CSI-2 Receiver IP Core is delivered as encrypted VHDL. It is optionally available as VHDL source code. It is compatible with Xilinx Artix7, Kintex7, Zynq7 and Ultrascale+ FPGAs. The MIPI CSI-2 Receiver IP Software library is delivered as an object file. It is optionally available as C source code.

Block diagram
Block diagram

The core is made of five main parts. The lane management together with the packet engine receive parallel byte lanes, extract control information, implement lane alignment and byte reordering, and finally provide aligned payload byte streams. The pixel unpacker extracts pixel data types out of these byte streams. The output pixel clock adjustment converts the pixel stream into the output clock domain. The control interface contains a set of control and status registers accessible by a CPU using the AXI4-Lite slave interface.

Resource Usage
Resource Usage