A Sensor to Image product
Top Level Design
The first component of the IP Core is the Top Level Design. It is an interface between external hardware (imager, sensors, GigE PHY) and FPGA internal data processing. We deliver this module as VHDL source code that can be adapted to custom hardware.
A Framebuffer interfaces to the FPGA vendor specific memory controller. The framebuffer allows for frame buffering and image packeting. This is necessary to implement the packet resend function. This module typically uses external memory, but could also be realized with limited functionality by the FPGA’s internal memory.
Some parts of the design are delivered as binary files only (for example the GigE Vision control protocol library), while other parts are delivered as source code. The design framework comes with all the necessary design files and cores, Vivado or Quartus project files. It is configured as a GigE Vision camera system with a configurable test pattern generator. This system is delivered as a reference design for an off-the-shelf evaluation board. The reference design uses the AMD or Intel development tools (not in the scope of delivery).
GigE Vision IP Core Description
GigE Vision is a standard communication protocol for vision applications based on the well-known Ethernet technology. It allows easy interfacing between GigE Vision devices and PCs running TCP/IP protocol family. Sensor to Image offers a set of IP cores and a development framework to build FPGA-based transmitter products using the GigE Vision interface. Due to the speed of GigE Vision, especially at speeds higher than 1 Gbps, senders require a fast FPGA-based implementation of the embedded GigE core. The GigE Vision core set is compatible with AMD 7 Series devices (and newer), Intel Cyclone V devices (and newer) and Microchip PolarFire.
Video Acquisition Module
The Video Acquisition Module of the reference design simulates a camera with a test pattern generator. This module is delivered as VHDL source code, which has to be replaced by a sensor interface and pixel processing logic in the final camera design.
GigE Packet Composer
The GigE Packet Composer generates the final stream packets with all headers required by the GigE Vision transport layer. The GigE Packet Composer sends all data to the Ethernet MAC and implements the high-speed GigE Vision Streaming Protocol (GVSP).
Broad Support of FPGA Development Kits
Sensor to Image's FPGA IP Cores are delivered as fully-working reference designs on an FPGA development kit. We support a wide range of off-the-shelf kits from AMD, Intel and Microchip.
Supplied Reference design
Fully-functioning Reference Design: S2I’s FPGA solutions are delivered as a self-contained, fully-functioning reference design that is running on an agreed common platform along with FPGA IP Cores. This minimizes development time and allows for top-notch performance at a small footprint, while leaving enough flexibility to customize the design. Sensor to Image cores are compact and leave enough space in the FPGA for your application.
Sphinx SDK included
A feature-rich software toolkit that provides the building blocks to quickly and easily design high-performance video applications that use minimal CPU resources. This also includes a filter driver and acquisition library for Windows or Linux along with sample applications, including GigE Vision/ GenICam compliant viewer.
FPGA Integrated CPU
An FPGA integrated CPU (MicroBlaze, NIOS, ARM) is used for several non-time-critical network and configuration tasks and it runs the GigE Vision Control Protocol (GVCP). This software is written in C and can be extended by the customer.