Vision Standard IP Cores

GigE Vision, USB3 Vision, CoaXPress

At a glance
  • Compatible with AMD, Intel and Microchip Polarfire FPGAs
  • Compact, customizable
  • Delivered as working reference design
 
GigE Vision Device IP Core

GigE Vision Device IP Core for FPGA
 
GigE Vision Host IP Core

GigE Vision Host IP Core for FPGA
 
GigE Vision Host Software

Software Development Kit for GigE Vision compliant applications
 
GigE Vision Server

Software based GigE Vision Device Implementation
 
CoaXPress Device IP Core

CoaXPress Device IP Core for FPGA
 
CoaXPress Host IP Core

CoaXPress Host IP Core for FPGA
 
CoaXPress-over-Fiber Bridge Device IP Core

CoaXPress-over-Fiber Bridge Device IP Core for FPGA
 
CoaXPress-over-Fiber Bridge Host IP Core

CoaXPress-over-Fiber Bridge Host IP Core for FPGA
 
USB3 Vision Device IP Core

USB3 Vision Device IP Core for FPGA
 
USB3 Vision Host Software

Software Development Kit for USB3 Vision compliant applications
A Sensor to Image product
A Sensor to Image product

Video Acquisition Module

The Video Acquisition Module of the reference design simulates a camera with a test pattern generator. This module is delivered as VHDL source code, which has to be replaced by a sensor interface and pixel processing logic in the final camera design.

Reduced time to market

Machine vision camera suppliers reduce time to market with transport layer IP Cores, and rely on Sensor to Image to keep up with both technological and standards advancements.
To stream images from the camera to the host, several modern standards of vision transport layers exist. The most powerful ones (GigE Vision, USB3, CoaXPress, ...) may however appear complex and evolving. Compressing months of development work, Sensor to Image’s IP Cores enable machine vision companies to build FPGA-based products following these standards, delivering the highest possible performance in a small footprint while minimizing development time.

Working Reference Design

S2I’s Vision Standard IP Cores solutions are delivered as a working reference design along with FPGA IP cores. This minimizes development time and allows for top-notch performance at a small footprint, while leaving enough flexibility to customize the design. Sensor to Image cores are compact and leave enough space in the FPGA for your application.

FPGA Integrated CPU

An FPGA integrated CPU (MicroBlaze, NIOS, ARM, Risc V) is used for several non-time-critical control and configuration tasks with the CXP-Device/Host core. This software is written in C and can be easily extended by the customer.

Top Level Design

The first component of the IP Core is the Top Level Design. It is an interface between external hardware (imager, sensors, GigE Vision, USB3 Vision or CoaXPress PHY) and FPGA internal data processing. We deliver this module as VHDL source code that can be adapted to custom hardware.

MVDK Machine Vision Development Kit

Sensor to Image MVDK development kit is a flexible evaluation platform for machine vision applications.

  • support for CoaXPress host and device reference designs
  • support for GigE Vision host and device reference designs
  • support for USB3 Vision device designs
  • support for Sony IMX imager interface designs
  • support for various Enclustra FPGA modules with Intel and AMD FPGAs

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