USB3 Vision Device IP Core

S2I’s USB3 Vision FPGA solution is delivered as a fully-working reference design along with FPGA IP cores. This minimizes development time and allows for top-notch performance at a small footprint, while leaving enough flexibility to customize the design. Sensor to Image cores are compact and leave enough space in the FPGA for your application.

A Frame buffer interfaces to the FPGA vendor specific memory controller. The framebuffer allows for data buffering and image partitioning. This module typically uses FPGA’s internal memory, but alternatively external memory for levelling out longer communication delays between camera and PC can be used.

The USB3 Vision Streaming Protocol Packet Composer takes all data from the video source and builds the USB3 Vision streaming packets. It also handles all low-level communication to the USB3 PHY (Cypress FX3).

USB3 Vision is a standard communication protocol for vision applications based on the widely used USB 3.0 interface. As the protocol is standard and supports GenICam, it allows easy interfacing between cameras and PCs. Sensor to Image offers a set of IP Cores and a development framework to build FPGA-based products using the USB3 Vision interface. Due to the speed of USB3 Vision, senders and receivers require a fast FPGA-based implementation of the embedded USB core. USB3 Vision IP Cores are compatible with AMD 7 Series devices (and newer) and Intel Cyclone V devices (and newer).

Sphinx is a feature-rich software toolkit that provides the building blocks to quickly and easily design high-performance video applications that use minimal CPU resources. The toolkit also includes a USB3 Vision device driver and acquisition library for Windows or Linux along with sample applications, including a USB3 Vision/Genicam compliant viewer.

Sensor to Image's MVDK development kit is a flexible evaluation platform for machine vision applications. It supports USB3 Vision device designs for various Enclustra FPGA modules with Intel and AMD FPGAs.

A Cypress FX3 chip (with integrated ARM CPU and physical interface) is used to handle all USB3 initialization routines and USB3 Vision control channel communication.

The USB3 Vision IP Core has the option for the source code of the embedded USB3 Vision library running on the Cypress FX3 USB controller. This is useful to extend functionality for rarely-used optional USB3 Vision features or to better tailor hardware requirements.

The first component of the IP Core is the Top Level Design. It is an interface between external hardware (imager, sensors, USB3 PHY) and FPGA internal data processing. We deliver this module as VHDL source code and it can be adapted to custom hardware.

The Video Acquisition Module of the reference design simulates a camera with a test pattern generator. This module is delivered as VHDL source code, which has to be replaced by a sensor interface and pixel processing logic in the final camera design.