CoaXPress IP Core

用于 FPGA 的 CoaXPress IP 核

  • Compatible with AMD 7 Series (and newer) and Intel Cyclone V devices (and newer)
  • 与Microchip PolarFire初步兼容
  • 紧凑、可定制
  • 支持从 1 Gb/s 到 40 Gb/s 以上的速度
  • 提供工作参考设计

比较 购买地点

Sensor to image产品
Sensor to image产品


IP 核的第一个组件是顶层设计。它是外部硬件(成像器、传感器、CXP PHY)和 FPGA 内部数据处理之间的接口。我们提供此模块的 VHDL 源代码,可以针对自定义硬件进行改编。

CoaXPress 控制接口

CXP 控制接口从 CXP 控制通道收发所有数据,从 CXP PHY 发送/接收数据,并根据 CXP 规范实现控制通道。

用于 CoaXPress 的 MVDK 机器视觉开发套件
用于 CoaXPress 的 MVDK 机器视觉开发套件

Sensor to Image MVDK development kit is a flexible evaluation platform for machine vision applications. It supports CoaXPress host and device reference designs for various Enclustra FPGA modules with Intel and AMD FPGAs.

CoaXPress IP 核描述

CoaXPress is a standard communication protocol for vision applications based on widely used coaxial cables. It allows easy interfacing between cameras and frame grabbers and supports the GenICam software standard. Sensor to Image offers a set of IP cores and a development framework to build FPGA-based products using the CoaXPress interface. Due to the speed of CXP, senders and receivers require a fast FPGA-based implementation of the CXP core, preferably using embedded transceivers. CXP cores are compatible with AMD 7 series devices (and higher) and Intel Cyclone V devices (and higher).


参考设计的视频采集模块可模拟具有测试图案生成器的相机。此模块以 VHDL 源代码形式提供,须由相机设计中的传感器接口和像素处理逻辑代替。


FPGA 集成 CPU(MicroBlaze、NIOS、ARM)用于 CXP 接收器或发送器核上的一些非时间关键型控制和配置任务。该软件采用 C 语言编写,用户可自行扩展


S2I CXP FPGA 解决方案提供一套附带 FPGA IP 核的工作参考设计。这将最大限度缩短开发时间,并能以较小的尺寸实现一流的性能,同时保留足够的灵活性来定制设计。Sensor to Image 核非常紧凑,可在 FPGA 中为您的应用留出足够的空间。

CoaXPress 流接口

CXP 流接口接收从视频传感器输出到 CXP PHY 的所有数据。根据 CXP 规范,它在流通道上达到全速。


Some parts of the design are compiled files only (for example the CXP control protocol library), while other parts are source code. The design framework comes with all the necessary design files and cores, Vivado or Quartus project files. It is configured either as a CXP camera system with an optional CMOS imager, or as an embedded CXP host (receiver). This system is used as a reference design and evaluation board. The reference design uses the AMD or Intel development tools (not in the scope of delivery).