视觉标准IP核

The Video Acquisition Module of the reference design simulates a camera with a test pattern generator. This module is delivered as VHDL source code, which has to be replaced by a sensor interface and pixel processing logic in the camera design.

S2I’s Vision Standard IP Cores solutions are delivered as a working reference design along with FPGA IP cores. This minimizes development time and allows for top-notch performance at a small footprint, while leaving enough flexibility to customize the design. Sensor to Image cores are compact and leave enough space in the FPGA for your application.

An FPGA integrated CPU (MicroBlaze, NIOS, ARM) is used for several non-time-critical control and configuration tasks on the Vision Standard IP Cores. This software is written in C and can be extended by the customer.

The first component of the IP Core is the Top Level Design. It is an interface between external hardware (imager, sensors, GigE VisionThe first component of the IP Core is the Top Level Design. It is an interface between external hardware (imager, sensors, GigE Vision, USB3 VisionThe first component of the IP Core is the Top Level Design. It is an interface between external hardware (imager, sensors, GigE VisionThe first component of the IP Core is the Top Level Design. It is an interface between external hardware (imager, sensors, GigE Vision, USB3 Vision or CXP Vision PHY) and FPGA internal data processing. We deliver this module as VHDL source code that can be adapted to custom hardware.

Sensor to Image MVDK development kit is a flexible evaluation platform for machine vision applications.

• support for CoaXPress host and device reference designs
• support for GigE Vision host and device reference designs
• support for USB3 Vision device designs
• support for Sony IMX imager interface designs
• support for various Enclustra FPGA modules with Intel and Xilinx FPGAs