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CoaXPress-over-Fiber Bridge Device IP Core

CoaXPress-over-Fiber Bridge Device IP Core for FPGA

CXP to nGMII Bridge IP Core
Compatible with AMD 7 Series (and newer)
Compatible with Altera Cyclone/Arria 10/Agilex
Compatible with S2I and third-party CoaXPress Device IP Cores
Delivered as working reference design (when licensed with the S2I CoaXPress Device IP Core) and extensive simulation testbench
Datasheet
Where to buy
CoaXPress-over-Fiber Bridge Device IP Core
Euresys

© EURESYS S.A. - Subject to change without notice

12/18/2023

Datasheet

CoaXPress-over-Fiber Bridge Device IP Core

CoaXPress-over-Fiber Bridge Device IP Core for FPGA


  • CXP to nGMII Bridge IP Core
  • Compatible with AMD 7 Series (and newer)
  • Compatible with Altera Cyclone/Arria 10/Agilex
  • Compatible with S2I and third-party CoaXPress Device IP Cores
  • Delivered as working reference design (when licensed with the S2I CoaXPress Device IP Core) and extensive simulation testbench

Main benefits

Other benefits

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CoaXPress-over-Fiber Bridge Device IP Core

Architecture

CoaXPress-over-Fiber Bridge IP Core

The CoaXPress-over-Fiber Device Bridge IP Core allows to connect a CoaXPress Device IP Core to an nGMII (10/25 Gbps Media Independent Interface) bus inside an FPGA. nGMII, as defined in IEEE Std 802.3 Clause 46, is the main access to the 10/25G Ethernet physical layer. The generic nature of this interface facilitates mapping the CoaXPress signaling into the PCS/PMA Ethernet sublayers. The IP converts CoaXPress control and streaming packets to nGMII packets going towards an Ethernet PCS/PMA block.

Main benefits

Other benefits

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