A Sensor to Image product
Top Level Design
The first component of the IP Core is the Top Level Design. It is an interface between external hardware (imager, sensors, GigE PHY) and FPGA internal data processing. We deliver this module as VHDL source code that can be adapted to custom hardware.
GigE Packet Composer
The GigE Packet Composer sends all data to the Ethernet MAC and implements the high-speed GigE Vision Streaming Protocol (GVSP).
MVDK Machine Vision Development Kit for GigE Vision
Sensor to Image MVDK development kit is a flexible evaluation platform for machine vision applications. It supports GigE Vision host and device reference designs for various Enclustra FPGA modules with Intel and Xilinx FPGAs.
GigE Vision IP Core Description
GigE Vision is a standard communication protocol for vision applications based on the well-known Ethernet technology. It allows easy interfacing between GigE Vision devices and PCs running TCP/IP protocol family. Sensor to Image offers a set of IP cores and a development framework to build FPGA-based products using the GigE Vision interface. Due to the speed of GigE Vision, especially at speeds higher than 1 Gb/s, senders and receivers require a fast FPGA-based implementation of the embedded GigE core. GigE Vision cores compatible with Xilinx 7 Series devices (and higher) and Intel/Altera Cyclone V devices (and higher).
Video Acquisition Module
The Video Acquisition Module of the reference design simulates a camera with a test pattern generator. This module is delivered as VHDL source code, which has to be replaced by a sensor interface and pixel processing logic in the camera design.
FPGA Integrated CPU
An FPGA integrated CPU (MicroBlaze, NIOS, ARM) is used for several non-time-critical network and configuration tasks and it runs the GigE Vision Control Protocol (GVCP). This software is written in C and can be extended by the customer.
Working Reference Design
S2I’s GigE Vision FPGA solution is delivered as a working reference design along with FPGA IP cores. This minimizes development time and allows for top-notch performance at a small footprint, while leaving enough flexibility to customize the design. Sensor to Image cores are compact and leave enough space in the FPGA for your application.
The Framebuffer core interfaces to the FPGA vendor specific memory controller. The framebuffer allows frame buffering and image partitioning. This is necessary to implement the packet resend function.
Some parts of the design are compiled files only (for example the GigE Vision control protocol library), while other parts as source code. The design framework comes with all the necessary design files and cores, Vivado or Quartus project files. It is configured either as a GigE Vision camera system with an optional CMOS imager, or as an embedded GigE Vision host (receiver). This system is used as a reference design and evaluation board. The reference design uses the Xilinx or Intel/Altera development tools (not in the scope of delivery).