MultiCam 6.19
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- Unterstützung für Windows 11
- Unterstützung der neusten Linux-Distributionen und Kernels
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Framegrabber für 1 Camera Link-Kamera in Full-Konfiguration mit Unterstützung extra langer Kabel
© EURESYS S.A. - Subject to change without notice
8/14/2024 Datasheet Framegrabber für 1 Camera Link-Kamera in Full-Konfiguration mit Unterstützung extra langer Kabel
Main benefitsOther benefitsSpezifikationenMechanical
Host bus
Camera / video inputs
Area-scan camera control
Line-scan camera control
On-board processing
General Purpose Inputs and Outputs
Software
Environmental conditions
Certifications
Ordering Information
Offices
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Camera Link ist eine semi-parallele/semi-serielle Punkt-zu-Punkt-Datenschnittstelle, die mehrere LVDS-Paare (Low-Voltage Differential Signaling) und ein oder zwei 26-polige Steckverbinder MDR-26 oder SDR-26 verwendet. Es sind verschiedene Camera Link-Konfigurationen verfügbar, von einer Basiskonfiguration mit einem Anschluss/Kabel und einer Bandbreite von bis zu 2 Gbit/s bis hin zu einer 80-Bit-Konfiguration (Deca) mit zwei Anschlüssen/Kabeln und einer Bandbreite von 6,8 Gbit/s (850 MB/s). Zusätzlich zur Bildübertragung bieten vier Kamerasteuerungssignale eine direkte Steuerung der Kamera ohne Latenz.
PCI Express card
Standard profile, half length, 4-lane PCI Express card
Air-cooling, fanless
For insertion in a standard height, 4-lane or higher, PCI Express card slot
'BASE' on bracket:
26-position Shrunk Delta Ribbon (SDR) socket
Camera Link Base connector
'MEDIUM/FULL'
26-position Shrunk Delta Ribbon (SDR) socket
Camera Link Medium/Full/80-bit connector
'EXTERNAL I/O' on bracket:
26-pin 3-row high-density female sub-D connector
I/O lines and power output
'INTERNAL I/O' on PCB:
26-pin 2-row 0.1" pitch pin header with shrouding
I/O lines and power output
'POWER INPUT' on module:
4-pin MOLEX power socket
12 VDC power input for PoCL camera and I/O power
PCB L X H: 167.65 mm x 111.15 mm, 6.6 in x 4.38 in
Net weight: 135 g [4.8 oz]
Gross weight: 236 g [8.3 oz]
2.5 GT/s (PCIe 1.0)
PCI Express 1.0
4 lanes
1024 bytes
32- and 64-bit
1,024 MB/s
Up to 833 MB/s for a PCI Express payload size of 256 bytes and 64-bit addressing
Up to 844 MB/s for a PCI Express payload size of 256 bytes and 32-bit addressing
Up to 754 MB/s for a PCI Express payload size of 128 bytes and 64-bit addressing
Up to 780 MB/s for a PCI Express payload size of 128 bytes and 32-bit addressing
Max. 9.9 W; Typ. 8.2 W (1.0 A @ 3.3V;0.41 A @+12V)
Camera Link
Base, Medium, Full, 72-bit, 80-bit
Note: Unpacking to 16-bit and image reconstruction are not available for the 8x 10-bit variant of the 80-bit configuration.
From 20 MHz up to 85 MHz
Two independent PoCL SafePower compliant controllers with overload, over-voltage and short-circuit protection
ECCO+
Grayscale and color (RGB and Bayer) area- and line-scan cameras
One 80-bit / 72-bit / Full / Medium / Base configuration camera
Mono8, Mono10, Mono12, Mono14, Mono16
BayerXX8, BayerXX10, BayerXX12, BayerXX14, BayerXX16 where XX = GR, RG, GB, or BG
RGB8, RGB10, RGB12, RGB14, RGB16
Camera Link 2.0
85 MHz
1
80-bit
Yes
PoCL
6.8 Gbit/s (850 MB/s)
Two Shrunk Delta Ribbon (SDR) Miniature Camera Link (MiniCL)
Precise control of asynchronous reset cameras, with exposure control.
Support of camera exposure/readout overlap.
Support of external hardware trigger, with optional delay and trigger decimation.
Accurate control of the strobe position for strobed light sources.
Support of early and late strobe pulses.
Precise control of start-of-scan and end-of-scan triggers.
Support of external hardware trigger, with optional delay.
Support of infinite acquisition, without missing line, for web inspection applications.
Support for quadrature motion encoders, with programmable noise filters, selection of acquisition direction and backward motion compensation.
Rate Converter tool for fine control of the pixel aspect ratio.
Rate Divider tool
Accurate control of the strobe position for strobed light sources.
Advanced interpolation method using average and median functions on a 3x3 kernel
Up to 225 MPixel/s
128 MB (64 MB for image data)
Unpacking of 10-/12-/14-bit to 16-bit with selectable justification to LSb or MSb
Monochrome: 8-bit, 10-bit or 12-bit per pixel, up to 1000 MPixel/s
RGB: 3x8-bit, 3x10-bit or 3x12-bit per pixel, up to 250 MPixel/s
Non-isolated, +5V, 1A and +12V, 1A, with electronic fuse protection
10 I/O lines:
2 differential inputs (DIN)
4 isolated inputs (IIN)
4 isolated outputs (IOUT)
The input lines can be used by the acquisition channel as:
Camera frame trigger source (area-scan only)
Acquisition sequence trigger source (area-scan only)
Camera line trigger source (line-scan only)
Page acquisition trigger source (line-scan only)
Page acquisition end trigger source (line-scan only)
(Quadrature) motion encoder input (line-scan only)
The IOUT 1 output line can be used by the acquisition channel as:
Illumination strobe output
All the input lines can be used as general purpose inputs
All the output lines can be used as general purpose outputs
DIN: High-speed differential inputs, up to 5 MHz, compatible with ANSI/EIA/TIA-422/485 differential line drivers and complementary TTL drivers
IIN: Isolated current-sense inputs with wide voltage input range up to 30V, compatible with totem-pole LVTTL, TTL, 5V CMOS drivers, RS-422 differential line drivers, potential free contacts, solid-state relays and opto-couplers
IOUT: Isolated contact outputs compatible with 30V / 100mA loads
NOTE: IIN and IOUT lines provide a functional isolation grade for the circuit technical protection. It does not provide an isolation that can protect a human being from electrical shock!
Glitch removal filter available only on input lines used as trigger sources
Configurable with five time constants:
100 ns, 500 ns, and 2.5 µs for trigger / page trigger / page end trigger sources
40 ns, 100 ns, 200 ns, 500 ns, 1 µs, 5 µs, 10 µs for line trigger sources
Yes
MultiCam 32- and 64-bit binary libraries (Windows and Linux), for ISO-compliant C/C++ compilers
Microsoft Windows 10, 8.1, 7 for x86 (32-bit) and x86-64 (64-bit) processor architectures
Linux for x86 (32-bit) and x86-64 (64-bit) processor architectures
Refer to release notes for details
0 °C to +50 °C / +32 °F to +122 °F
10% to 90% RH non-condensing
-20 °C to +70 °C/ -4 °F to +158 °F
10% to 90% RH non-condensing
Korean Radio Waves Act, Article 58-2, Clause 3
PCB compliant with UL 94 V-0
European Union Directive 2015/863 (ROHS3)
European Union Regulation 1907/2006
Must be disposed of separately from normal household waste and must be recycled according to local regulations
European Council EMC Directive 2014/30/EU
United States FCC rule 47 CFR 15
EN 55022:2010 / CISPR 22:2008 Class B
EN 55032:2015 / CISPR 32:2012 Class B
FCC 47 Part 15 Class B
EN 55024:2010 / CISPR 24:2010
EN 55035:2017 / CISPR 35:2016
EN 61000-4-2:2009
EN 61000-4-3:2006
EN 61000-4-4:2004
EN 61000-4-5:2014
EN 61000-4-6:2014
1626 Grablink Full XR
3305 C2C SyncBus Cable
3306 C2C Quad SyncBus Cable