Learn more about our product features:
 

USB3 Vision IP Core

USB3 Vision IP Core for FPGA

At a glance
  • Compatible with Xilinx 7 Series (and higher) and Intel/Altera Cyclone V devices (and higher)
  • Compact, customizable
  • Delivered with a working reference design

USB3 VISION IP CORE Datasheet

Compare Where to buy


A Sensor to Image product
A Sensor to Image product


Top Level Design

The first component of the IP Core is the Top Level Design. It is an interface between external hardware (imager, sensors, USB3 PHY) and FPGA internal data processing. We deliver this module as VHDL source code and it can be adapted to custom hardware.


Framebuffer Core

The Framebuffer core interfaces to the FPGA vendor specific memory controller. The framebuffer is used for leveling out communication delays between camera and PC.


MVDK Machine Vision Development Kit for USB3 Vision
MVDK Machine Vision Development Kit for USB3 Vision

Sensor to Image MVDK development kit is a flexible evaluation platform for machine vision applications. It supports USB3 Vision device designs for various Enclustra FPGA modules with Intel and Xilinx FPGAs.


USB3 Vision IP Core Description

USB3 Vision is a standard communication protocol for vision applications based on the widely used USB 3.0 interface. As the protocol is standard and supports GenICam, it allows easy interfacing between cameras and PCs. Sensor to Image offers a set of IP cores and a development framework to build FPGA-based products using the USB3 Vision interface. Due to the speed of USB3 Vision, senders and receivers require a fast FPGA-based implementation of the embedded USB core. USB3 Vision cores compatible with Xilinx 7 Series devices (and higher) and Intel/Altera Cyclone V devices (and higher).


Video Acquisition Module

The Video Acquisition Module of the reference design simulates a camera with a test pattern generator. This module is delivered as VHDL source code, which has to be replaced by a sensor interface and pixel processing logic in the camera design.


Cypress FX3

A Cypress FX3 chip (with integrated ARM CPU and physical interface) is used to handle all USB3 initialization routines and USB3 Vision control channel communication.


Working Reference Design

S2I’s USB3 Vision FPGA solution is delivered as a working reference design along with FPGA IP cores. This minimizes development time and allows for top-notch performance at a small footprint, while leaving enough flexibility to customize the design. Sensor to Image cores are compact and leave enough space in the FPGA for your application.


USB3 Vision Streaming Protocol Packet Composer

The USB3 Vision Streaming Protocol Packet Composer takes all data from the video source and builds the USB3 Vision streaming packets. It also handles all low-level communication to the USB3 PHY.


Custom Configuration

Some parts of the design are compiled files only (for example the USB3 Vision control protocol library), while other parts are source code. The design framework comes with all the necessary design files and cores, Vivado or Quartus project files. It is configured as a USB3 Vision camera system with an optional CMOS imager. This system is used as a reference design and evaluation board. The reference design uses the Xilinx or Intel/Altera development tools (not in the scope of delivery).