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Camera Link image acquisition and pre-processing
for color AREA-SCAN inspection
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The Grablink Quickpack CFA -Color Filter Array- offers a set of dedicated on-board preprocessing functions to speed
up image processing for applications such as PCB, food or pharmaceutical inspection without loading the host CPU.
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Image pre-processing functions accelerated by the FPGA
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All operators are compatible with 8-, 10- and 12-bit input images.
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 A Bayer Pattern decoder computes the R,G and B components of the image
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A white balance operator
 - The white balance parameters can be specified by the user or computed automatically from the image.
- They can be computed continuously (on each image) or once only (under user control).
- Moreover, they can be computed from automatically selected white pixels in the image, or from a user-specified region of interest.
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A luminance blender computes the Y component of the image
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Four 16-bit x 16-bit LUT operators on R, G, B and Y channels
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Image acquisition and transfer
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Support of Base configuration for AREA-SCAN single or dual-tap cameras
- Bayer pattern color
- Also compatible with monochrome and RGB cameras
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9 various I/O lines available on external and internal connectors
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CAMERA
COMPATIBILITY
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Monochrome or Bayer
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Color RGB
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single-tap
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dual-tap
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quad-tap
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single-tap
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Tap configuration
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Base_1T8, Base_1T10, Base_1T12, Base_1T14, Base_1T16
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Base_2T8, Base_2T10, Base_2T12, Base_2T14B2, Base_2T16B2
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Base_4T8B2
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Base_1T24, Base_1T24B3, Base_1T30B2, Base_1T36B2, Base_1T36B3, Base_1T42B2, Base_1T42B3, Base_1T48B2, Base_1T48B3
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Camera Link
configuration
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Base
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1 tap x (8-10-12-14-16 bits)
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2 taps x (8-10-12 bits)
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1 tap x (24 bits)
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Extended Base*
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2 taps x (14-16 bits)
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4 taps x (8 bits)
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1 tap x (24-30-36-42-48 bits)
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* Multiplex tap.
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Output format
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- 8 -, 10-, 12- and 16-bit components (R, G, B and Y)
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- Wide range of formats are available in the following classes:
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• monochrome
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• four packed R G B a components
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• Bayer CFA
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• four packed R G B Y components
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• three packed R G B components
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• three packed R G B components + Y component
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• three planar R G B components
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• three planar R G B components + Y component
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| Raw image |
Bayer pattern decoder |
White balance |
Luminance blender |
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Form factor: Conventional PCI
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64-bit, 66 MHz, 3V/5V signaling
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Image Resolution
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Up to 4096 by 4096
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PoCL Safe Power compliant
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Form factor: PCI Express
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Full-height, half-length, x4
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Image Resolution
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Up to 7616 x 4096
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Trigger decimation: it controls the acquisition rate from an electrical signal by setting a programmable decimation factor.
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 Top
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Euresys products comply with the RoHS Directive
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Copyright © 1989 - 2009 Euresys s.a. All rights reserved - See Euresys Terms and Conditions
For questions about Euresys Company and Products please contact info@euresys.com
RPM Liège 0437408137 - TVA BE 437 408 137 - RC Liège 168 568
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Quickpack CFA boards
Image pre-processing accelerated by the FPGA